The invention relates generally to a method for fabricating a semiconductor memory device and, more particularly, to a method for fabricating a semiconductor memory device capable of reducing contact resistance.
The sizes of contact holes of semiconductor memory devices have decreased with the increase in degree of integration of semiconductor memory devices. A dynamic random access memory (DRAM) device employs a landing plug contact to electrically connect an impurity region of a semiconductor substrate and a conductive layer thereabove, e.g. a bit line or a storage node. Thus, the landing plug contact is formed by filling a landing plug contact hole between word lines formed with gate stack with a conductive material wherein the bit line contact and the storage node contact are connected to the landing plug contact. In general, the landing plug contact comprises a polysilicon layer.
However, due to the decrease in the design rule according to the increase in the degree of integration, an area of an active region in which active devices such as transistors are arranged is reduced in size and, as the result, an area of the landing plug contact hole in which the landing plug contact is formed tends to be more and more reduced in size. As the area of the landing plug contact hole is reduced in size, the resistance of the landing plug contact is increased, while an operation current is reduced. Particularly, in a case of a bit line contact in which contact resistance is an important factor, the increase in the contact resistance obstructs generation of an efficient amount of operation current and this causes a deterioration of properties of a memory device requiring high speed operation.
As a method to overcome the problem resulting from the increase in the contact resistance, impurity ions may be implanted after forming the landing plug contact. In order to dope impurities to the landing plug contact, P-type impurities are doped by ion implantation or plasma doping after a conductive layer is deposited. However, the method of doping the conductive layer by ion implantation is inefficient since there is no mass-productivity, as 30 minutes or more are required per wafer to implant a large amount of P-type dopants to the conductive layer. The plasma doping can ensure the mass-productivity, but has a problem in that distribution of the contact resistance (Rc) in a semiconductor wafer deteriorates due to irregularity of plasma itself.
FIG. 1 is a graph showing distribution of contact resistance across the diameter of a wafer when doping a bit line contact using plasma doping and ion implantation, respectively. The X-axis represents the diameter of a semiconductor substrate and the Y-axis represents a magnitude of resistance per unit area.
Referring to FIG. 1, near the periphery of the semiconductor substrate, the distribution of the contact resistance is up to 200% is shown in Case 120 (doping the bit line contact by the plasma doping) as compared to Case 110 (doping the bit line contact by the ion implantation).
Therefore, it is necessary to provide a method capable of improving the distribution of the contact resistance (Rc) in the semiconductor substrate while effectively reducing the contact resistance using the plasma doping.